Previous: Specification of Operands.
Up: Instruction Set
Next: Control Flow Instructions.
Previous Page: Specification of Operands.
Next Page: Control Flow Instructions.
The other instructions should fit quite well into the format of the register--to--register instruction, or at least introduce as few different formats as possible. The load instruction fits well into this format: dest := Mem[src1 AluOp src2]
The register file is not capable of delivering three source operands in a single cycle. Therefore, the store instruction Mem[src1 AluOp Imm] := src2 can be realized by taking the unused dest field of the instruction as an immediate value.