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Specification of Operands.

Besides the conventional register addresses for the specification of operands, stack accesses need to be realized in CAST. Therefore, at least 7 bits are required to specify an operand: either all 7 bits refer to a normal register (padded with 0), or they are split up in a 2-bit stack number and a 5-bit index. Additionally, a distinction between a conventional register and a stack access must be made in the instruction. Instead of using different instruction groups, another bit is used for this purpose, thus allowing the mixing of registers and stack elements in a single operation.

In destination position another distinction must be made: it is either possible to use an indexed write or a create-frame operation. This gives a total of nine bits to specify a destination. The two most significant bits determine, if a normal or special register (see below) is the destination, or a write indexed or a create-frame stack operation shall be performed. Source 1 is similarly encoded: instead create-frame a delete-frame operation may be specified. For source 2 a normal register, an indexed read or an immediate value can be specified.

This gives a total of 27 bits (3 * 9) to specify the three operands of a register--to--register instruction. With only 5 bits left in a 32-bit word, the instruction encoding is nearly impossibly without introducing some strange formats. Therefore, a 40-bit instruction width has been chosen, leading to a consistent 40-bit architecture. A register--to--register instruction has the following format:

The first field ''Primary Opcode`` specifies the instruction type, the second the destination (according to above specifications), the special field will be discussed later on, AluOp denotes the operation of the ALU and src1, src2 specify the source operands.

To generate 32-bit constants, two instructions must be used since a ``normal'' immediate value is only 8 bits wide. The upper 24 bits can be set with the Set-Immediate-High instruction (abbreviated SImmH).