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Exception Handling

Exceptions can be divided into two types: traps are caused by internal exceptional events like stack overflow or tag error; interrupts are external generated signals from other devices like memory controllers or DMA devices.

In CAST, the selection of an exception handler is done by a 5-bit vector number, which is shifted 5 bits to the left and filled up with leading zeros. This allows the usage of 32 instructions for each exception handler without any jump.

The interrupts in CAST are Reset and Illegal Address (data or instruction), but the exception handling can be easily expanded for further types. Interrupts are polled at the end of each cycle, traps are detected in the corresponding pipeline stage. Stack over/underflow traps may occur in the decode stage, but are delayed to the end of the execute stage to simplify trap handling. If an exception is raised, the following operations are performed:

• the flags EnableTrap and NoFreeze are cleared, thus disabling the PC--chain and further exceptions,
• the instructions in the pipeline stages and are annulled,
• the top-pointers and the flag are restored to their original values they had before the execution of the trapped instruction,
• the appropriate exception handler address is determined and processing continues at this address.

If there is more than one exception, the one with the highest priority is taken, whereas the others are discarded. Thus, the ignored exception must occur again to be recognized. This is an appropriate approach, since some exceptions occur only due to others, such that the handling of the first exception will remove their cause. For example a stack underflow can produce also an integer trap, because the stack element given to the tag check unit is not valid. The underflow handler will resolve the situation such that the integer trap does not reoccur. A stack move could produce a stack underflow and an overflow, which will be handled sequently. After the trap handler for the underflow has been executed (which has a higher priority than overflow traps), the instruction will be reexecuted and trap again, whereas the stack overflow will be treated.

The pipelining of the processor complicates the handling of exceptions. The state of computation should be changed only in the write--back stage of the pipeline, since exceptions are taken at the end of the execute stage. This cannot be accomplished without affecting functionality. The stack operations must be performed at the end of the decode stage to guarantee a useful behavior. This involves the top-pointers and the ZSt flag, which must be backed up for two cycles. If an exception occurs, the registers are restored from the second backup value, thus reestablishing the correct situation. The exception handling mechanism is kept as simple as possibly to service the stack traps very fast. This is necessary for a competitive performance of the processor.