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Memory Interface

CAST has a Harvard architecture, i.e. data and instruction memory are conceptually separated. All memory accesses are performed with full 40-bit words. All addresses are word addresses, therefore no alignment restrictions as in other system are necessary.

Since the timing of memory accesses does not fit into the four--stage pipeline, an asynchronous memory interface has been chosen. The execution of the next instructions continues if they do not depend on the result of an outstanding load or are memory accesses themselves. In either of the latter cases the pipeline is stopped and the processor waits for the end of the memory access.