Previous: Tagged Data
Up: The Architecture of CAST
Next: Memory Interface
Previous Page: Tagged Data
Next Page: Memory Interface

Program Counter Unit

Most RISC processors with delayed--branches do not allow two consecutive branch instructions, since they are not able to restart such a sequence properly. Since CAST has two delay slots, a program counter for each stage of the pipeline is necessary to handle each possible trap in any combination of instructions correctly. Therefore, the program counter unit consists of the following registers: PCL1 contains the address of the instruction being fetched from instruction memory, PCL2 contains the next address in sequence, and the four registers of the PC--chain which are used to restart the normal program execution after a trap. The PC--chain is controlled by the so--called NoFreeze flag: if this flag is cleared, any further updates of the registers in the buffer are suppressed. This flag is cleared, if an exception is processed (see 0.2.7).