Master thesis proposals

Last Update 1999-11-14

None of these proposals are available anymore.

Proposals:

Design and Implementation of a Compiler for K2

No longer available.

K2 is a coordination language for distributed computing. In a first step, a compiler needs to be specified and implemented which is able to translate textual specifications of process communication structures into executable code. There are template for each kind of process type available which can serve as a basis for the straightforward implementation. In a second step, the compiler should perform several optimizations to minimize the runtime overhead and offer an acceptable performance.

Required knowledge: C, compiler construction, distributed computing, message passing.

Design and Implementation of a graphical Editor for K2

No longer available.

K2 is a coordination language for distributed computing. A graphical editor for K2 must offer: Easy ways to specify hierarchical process systems, interaction with the compiler and runtime system (for debugging, stepwise execution, etc). The editor should be based on available software for simple implementation and portability.

Required knowledge: C, XWindows, GUI

Design and Implementation of an Analysis Tool for K2

No longer available.

K2 is a coordination language for distributed computing. It allows for the formal analysis of process systems. This analysis should be supported by easy-to-use tools. Such a tool has to be designed and implemented. It is based on formal methods available for Petri-Nets. Moreover, the tools should offer (in conjuction with the compiler) means for debugging (e.g., by stepwise execution) of process systems.

Required knowledge: C, Petri-Nets, Formal Methods

Design and Implementation of a Reorganizer for a RISC processor

No longer available.

As part of a larger project the RISC processor Fast with a unique stack system has been developed. Two compilers are available for it: one for KiR (Kiel Reduction Language) and one for C. The processor puts some restrictions on the order of instruction execution which are caused by the latencies of some instruction types. For our processor these restrictions are mainly:

The goal of a code reorganization (scheduling) is to minimize the performance penalty caused by these restrictions. Instead of putting NOOPs into the delay slots, useful instructions must be moved into these slots.

There is one reorganizer available which only performs a subset of the possible code scheduling techniques. For some benchmarks the percentage of executed NOOPs is up to 45 per cent.

Therefore more sophisticated techniques for code scheduling must be used. Either the reorganizer or the compiler can be modified for this purpose, or a new reorganizer can be written, if necessary.

Required knowledge: C, compiler construction, processor architecture, RISC- assembler.


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Claus Aßmann Please send comments to: <ca@sendmail.org>