A RISC processor with a unique stack system

is a 40-bit RISC processor which has been designed as a target architecture for the efficient execution of functional languages. It may equally well be used as a target for the compilation of imperative languages. To support the efficient implementation of untyped functional languages features a tagged architecture, a system of four stacks, of which two are interchangeable, and up to 128 general purpose registers. It has a rather conventional set of value-transforming three-address instructions, control flow and load/store instructions with very few addressing modes. has a Harvard architecture, i.e. conceptually separated instruction and data memory access paths, and a very restricted set of addressing modes. High performance is achieved by a four-stage instruction pipeline. To simplify its hardware implementation, provides two delay slots for branch and load instructions.

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